Static Timing Analysis (STA) is a key step in the design of high speed Very Large Scale Integrated (VLSI) circuits. STA is used to verify that a VLSI circuit-design performs correctly at a required frequency before it is released for chip manufacturing. A circuit-design must be timing closed prior to manufacturing. Timing closure refers to the process of designing and optimizing a circuit such that applied electrical signals can traverse through the circuit within specified timing constraints. STA guides and validates the completion of timing closure. During STA, a circuit-design is represented as a timing graph; the points in the design where timing information is desired constitute the nodes or timing points of this graph, while electrical or logic connections between these nodes are represented as timing arcs of the graph. STA is performed typically at the logic gate level using lookup-table based gate timing libraries and involves some runtime expensive circuit simulation for timing calculation of wires and gates using current source model based timing libraries.
With modern chip manufacturing technology scaling to sub-45 nanometers, VLSI designs are increasingly getting larger in terms of size and complexity. Application Specific Integrated Circuit (ASIC) designs contain several to a few hundred million logic gates. Performance centric designs, especially microprocessor designs, include custom circuit designed components to achieve aggressive frequency targets and can contain upwards of one billion transistors. STA of these designs ideally like to employ circuit simulators for obtaining accurate timing calculations. However, the run-time intensive nature of circuit simulation is impractical for large designs, especially where timing runs are made daily during the design cycle of the chip. In essence, static timing analysis of modern large circuits as a single flattened design is run-time prohibitive. This has led to the development of a hierarchical timing flow wherein a circuit design is partitioned into components. A component may be partitioned further into sub-components in a recursive fashion. As an example, a typical microprocessor design is partitioned into several components called cores, each core is partitioned into components termed units, and each unit is partitioned into components termed macros. Illustratively, a core level of hierarchy can contain a set of units connected using wires and additional gates that may not be part of any component. Similarly, a unit level of hierarchy can contain a set of macros connected using wires and additional gates that may not be part of any component. For ease of notation, the term “component” will be used in this invention to refer to a sub-component or component (e.g. a macro, unit, or the core).
Referring to FIG. 1, it illustrates a unit component containing two sub-components (macros), namely, Macro-1 and Macro-2, and additional gates and wires. In a hierarchical timing flow, STA and timing closure for each component is performed in isolation or “out of context” (OOC). At this stage, the component is not connected to any other part of the circuit outside its scope. This is followed by the generation of a timing “abstract” that reflects in a simpler form, the timing characteristic of the component. A timing abstract could either be a pruned version of the component or a single gate timing model of the component. As an example of the former style of abstract, internal latch to latch paths of the component are deleted from the design in the abstract model. Known in the present art is described a process of generating the latter style of abstract while accounting for environmental and chip manufacturing variations. The primary objective of creating an abstract is to make the timing model of the component simpler.
Components are next represented using their abstracts at the parent level(s) of hierarchy. The hierarchical timing approach enables fast timing analysis and productivity at the parent level, since the abstract models are simpler and allow re-use. The benefits are significantly highlighted when multiple instances of a component are used at a level since the flow avoids separate static timing analysis for each instance of the full component.
FIG. 2 illustrates a component 200 with two primary inputs and one primary output pin. The component contains three latches, namely, L1, L2 and L3. This component is timed at the out-of-context level (not connected to the parent level of hierarchy), and then an abstract 201 of the component is generated. In this illustrative example, the internal latch to latch path from L1 to L3 is pruned in the abstract model.
A component's abstract is typically generated post timing closure and is then used at the parent level of hierarchy. However, timing closure of the component is dependent on the timing assertions at its boundary (primary input and primary output) pins. As an example, timing closure for a data path starting from a primary input (PI) of a component and leading to either a latch or a primary output (PO) is therefore dependent on when the electrical signal reaches the PI, which in turn is known accurately only at the parent level of hierarchy. This establishes a loop-like situation, wherein an abstract depends on boundary assertions from the parent level, and assertions at the parent level are dependent on the abstract. One way to solve this “chicken and egg” problem is to use some default guard-banded assertions at the cost of “over-design”. The alternative approach involves a feedback assertion process, wherein multiple iterations of abstracts are generated during the chip design life-cycle. In each iteration of using an abstract at the parent level of hierarchy, assertions for the component being represented by its abstract are generated, and are subsequently used to perform STA and timing closure of the component. This is followed by the generation of a new abstract for the component post timing closure using assertions from the prior version of the abstract. The new abstract is then used for the next iteration of feedback assertion generation.
FIG. 3 illustrates a parent level of hierarchy wherein component 300 contains an abstract of a sub-component. A set of two numbers is shown on certain pins in the design, and denote the {arrival-time (AT), required-arrival-time (RAT)}, respectively, for the corresponding pin. The source pin of the path that ends at pin DATA of the abstract has an arrival time of 10 units as shown in the figure. Assuming the path delay to be 5 units, it is observed that the pin DATA has an AT of (10+5)=15 units. Since the pin DATA has a RAT of 12 units, the RAT at the source pin of the path leading to DATA is (12−5)=7 units, as shown. Similarly, the CLOCK pin of the abstract has an AT of 2 units, while the AT of pin OUT is 18 units, implying that the path delay from CLOCK to OUT is (18−2)=16 units. Given this path delay and a RAT of 40 units at OUT, the RAT at CLOCK can be verified to be (40−16)=24 units. Finally, the last assumption in the figure is that the RAT at pin DATA is 10 units greater than the AT of pin CLOCK, thus being (2+10)=12 units. All timing values including slack (defined as the difference between RAT and AT) at the boundary pins of the abstract are shown in table 301 of FIG. 3. Based on this timing information at the parent level of hierarchy 300, prior art feedback assertions are generated by simply capturing the AT from inputs pins of the abstract, and the RAT from all output pins of the abstract. Thus, three numerical values are captured as feedback assertions and shown in table 302 of FIG. 3. Given these feedback assertions, and the timing characteristics of the abstract, all other timing values can be re-computed out-of-context, as described next.
FIG. 4 depicts the out-of-context timing computation and use of feedback assertions for a component 400. The abstract of this component is assumed to be the one used at the parent level of hierarchy 300 in FIG. 3. Prior to feedback assertions, the component 400 is assumed to have been timed using default (or older) assertions which are highlighted as underlined values in table 401. The table 401 contains all timing information computed using these assertions as well. The timing values are based on the assumptions made in the prior section, namely, the path delay from CLOCK to OUT is 16 units, and the RAT of pin DATA is 10 units greater than the AT of pin CLOCK. When feedback assertions (as illustrated in table 302 of FIG. 3) are applied to 400, the timing at various pins in the design is naturally updated, and the final results are shown in table 402. It is observed that updating assertions typically changes the AT, RAT, and slack on most pins of the design (except the asserted timing values). As an example, the slack at pin DATA changes from −1 units to −3 units with feedback assertions. This implies that the design needs to be optimized to compensate for a failing 3 units of timing as part of design closure. Not applying feedback assertions would wrongly imply design closure to only fix 1 unit of failing slack, and clearly illustrates the need for iterative feedback assertion based hierarchical design closure to ensure correct operation of the manufactured chip.
The main advantage of the feedback assertion process is that the most accurate data and clock signal timings at the boundary pins of the component's abstract (as observed during STA at a parent level of hierarchy) are used for timing closure of the component during its “out of context” timing. This enables accurate timing closure of boundary paths of the component. However, a new feedback assertion for a clock PI of the component also impacts the timing of internal latch to latch paths, which may be undesirable. As an example, applying feedback assertions 302 in FIG. 3 to component 400 in FIG. 4 updates the AT of pins CLOCK and OUT as shown in table 401 to new values as shown in table 402. While this aids correctly calculated slacks at these pins, the updated timing for this clock path (from CLOCK to OUT) has undesirable effects for component designers. Designers often perform timing closure of these internal paths up front, since these paths are conceptually independent of the boundary assertions under strict clock signal slew and skew restrictions. Component designers may even choose to use some guard banded default assertions for the timing closure of the internal latch to latch paths, and would like to avoid any timing changes or “disruptions” in these paths given new feedback assertions. The prior art method of generating feedback assertions provides new timing assertions for the clock PI pins and thus disrupts the timing of the internal latch to latch paths causing unnecessary optimization or changes in these paths as part of timing closure. A method of not using the new assertions for the clock PI pins, but using new assertions for non-clock PI pins will result in inconsistent timing of boundary paths, and may even lead to a false illusion of timing closure eventually resulting in a faulty manufactured chip design. Finally, a method of not using feedback assertions at all for out-of-context STA of the component is equally susceptible to yielding a faulty manufactured chip. This indicates a need for a method of generating feedback assertions that guarantee timing non-disruptions to the internal latch to latch paths, yet maintain the accuracy of timing closure in the boundary paths of the component.